1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC) and a method of controlling the same and, more particularly, to a semiconductor IC that includes a delay locked loop (DLL) circuit and a method of controlling the same.
2. Related Art
In general, a DLL circuit included in a semiconductor IC is commonly used to provide an internal clock signal having phases with a predetermined time earlier than a phase of a reference clock signal obtained by converting an external clock signal. The internal clock signal used in the semiconductor IC is delayed by a clock buffer and a transmission line, wherein a phase difference is generated between the internal clock signal and the external clock signal that results in increasing an output data access time. For this reason, the DLL circuit is used in order to increase an effective data output interval. Here, the DLL circuit performs a control operation such that the phase of the internal clock signal is a predetermined time earlier than the phase of the external clock signal.
The semiconductor IC implements a power down mode to decrease power consumption and stops power supply to internal areas during the power down mode. Similarly to the semiconductor IC, the DLL circuit also stops the operation of a clock input buffer during the power down mode, thereby stopping a clock generation operation. The DLL circuit includes a buffer control unit that determines whether or not to operate the clock input buffer according to whether or not a corresponding mode is in the power down mode.
In the semiconductor IC that implements the power down mode, when the power down mode is completed, a power supply voltage of the DLL circuit may be different from a power supply voltage before a corresponding mode shifts to the power down mode. The DLL circuit may be affected by electronic noise that occurs due to various factors in addition to the change in the power supply voltage of the DLL circuit. Thus, a phase and a duty cycle of a clock signal output from the DLL circuit may be different from a phase and a duty cycle before the corresponding mode shifts to the power down mode. As a result, performance of the DLL circuit can be deteriorated, thereby causing an error in the data output operation. In order to improve performance of the DLL circuit and secure reliability of the data output operation, it is required to prevent an erroneous operation from occurring.